Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a multiturn solenoidal inductor integrated in a semiconductor chip, such as those used for radio frequency (RF) communications. The present invention also relates to a method of fabricating the inventive multiturn solenoidal inductor.
Inductors integrated in semiconductor chips are normally fabricated in the shape of spirals in one BEOL (back-end-of-the-line) metallization level (plus vias to connect to and from the return arm). Because of the limited thickness of BEOL metallization layers (on the order of about 2 to about 4 microns), spiral inductors have a relatively high resistance (on the order of about 1-5 ohms or greater) for a given inductance value. Dual metal layers, with interconnecting vias, are sometimes utilized to reduce the spiral resistance. Because the inductance value is directly related to the length of the inductor trace, spiral inductors are limited to fairly small inductance values (on the order of about 20 nHenries or less), and occupy a fairly large area of the chip. Because the electromagnetic field of a spiral inductor is not confined, active devices are typically not allowed under the inductor, and thus spiral inductors occupy a lot of chip real estate.
Integrated solenoidal inductors can also be fabricated in the BEOL layers of a semiconductor chip. These devices have limitations arising from the high capacitive coupling between the solenoidal turns, which arises from the fact that the total thickness of the BEOL layers is very small, on the order of about 8 to about 10 microns, so the solenoidal turns are necessarily in close vertical proximity to each other. This close proximity also limits the cross-sectional area of the solenoid which directly limits the achievable inductance, since solenoidal inductance is directly related to cross-sectional area.
In view of the above drawbacks in the prior art, there is a continued need for developing a multiturn solenoidal inductor integrated in a semiconductor chip which overcomes the foregoing prior art problems.
One object of the present invention is to provide a multiturn solenoidal inductor integrated in a semiconductor chip.
A further object of the present invention is to provide a multiturn solenoidal inductor integrated in a semiconductor chip wherein the solenoid turns are sufficiently separate from each other, thereby reducing capacitive coupling between the solenoid turns.
A still further object of the present invention is to provide an integrated structure which contains solenoidal coils having large diameter cross-sections associated therewith.
An even further object of the present invention is to provide an integrated structure which has solenoidal coils having a large inductance value, yet occupy a small area of the chip.
These and other objects and advantages are obtained by providing solenoidal inductors integrated in a semiconductor chip wherein the solenoidal coil is partially embedded in a deep well (i.e., cavity) etched into the semiconductor chip. The term xe2x80x9cdeep wellxe2x80x9d as used herein denotes a cavity whose depth from an upper surface of the semiconductor chip is from about 10 to about 50 microns, preferably from about 20 to about 25 microns. This allows for large separation of solenoid turns, and thus reduces the capacitive coupling between the turns. Because the solenoidal coils of the present invention have a large diameter cross-section (on the order of about 25 to about 35 microns), the inventive coils can be made with a large inductance value and yet occupy a small area of the chip.
One aspect of the present invention thus relates to a semiconductor structure which comprises a solenoidal coil integrated with an integrated circuit (IC) chip, wherein said solenoidal coil is partially embedded inside a cavity formed in a substrate of said IC chip and partially in back-end-of-the-line layers of said IC chip.
In one embodiment of the present inventor, the solenoidal coil includes a magnetic core. In another embodiment of the present inventor, the solenoidal coil is in the shape of a toroid.
Another aspect of the present invention relates to an electrical transformer which comprises two solenoidal coils having a common magnetic core.
A still further aspect of the present invention relates to a method of fabricating the above-mentioned semiconductor structure. Specifically, the inventive semiconductor structure is fabricated by the following processing steps that include:
(a) forming one or more cavities in a substrate of an integrated circuit (IC) chip;
(b) forming a first dielectric material over said substrate including in said one or more cavities;
(c) removing said first dielectric material abutting said one or more cavities, while leaving said first dielectric material in said one or more cavities as a liner;
(d) forming a bottom coil element of a solenoidal coil in said one or more dielectric lined cavities;
(e) forming a second dielectric material over said substrate including said bottom coil element of said solenoidal coil;
(f) removing said second dielectric material over said substrate not containing said one or more cavities; and
(g) forming side coil elements and a top coil element of said solenoidal coil, wherein said top coil element is in electrical contact with said bottom coil element through said side coil elements.
In one embodiment of the inventive method, side coil elements are formed in step (d), and step (g) only includes formation of a top coil element.